A Parallel Fast Delayed Signal Cancellation Pll for Unbalanced and Distorted Grid Applications - Rojas-Lobos, F; Espina-Gonzalez, E; Diaz-Diaz, M (Institute of Electrical and Electronics Engineers Inc., 2019)
Phase-Locked Loops (PLLs) are a recognised alternative to detect grid frequency and phase angle, which allows grid synchronisation of distributed generation units. Nevertheless, frequency and phase angle estimation becomes complex in microgrid applications where unbalanced and distorted voltages are frequent. Therefore, a novel PLL structure for unbalanced and distorted grids is introduced in this paper. The proposed PLL is based on a parallel Fast Delayed Signal Cancellation (FDSC) structure. Several FDSC is connected in parallel to identify and eliminate different harmonics, allowing a fast and efficient fundamental frequency and phase angle estimation. Simulations results are presented to test the performance of the proposed PLL under severe imbalances and harmonics. © 2019 IEEE.